1 Introduction. - 1. 1 Problem Description. - 1. 2 Design Maturity Layers. - 1. 3 Proposed Approach. - 1. 4 Market Trends. - 1. 5 Organization of the Monograph. - 2 Background. - 2. 1 The Role of ASICs. - 2. 2 ASIC and ASSP design approaches. - 2. 3 Classification of approaches. - 2. 4 Model for Design Costs. - 2. 5 Conclusion. - 3 VHDL-Based Design. - 3. 1 VHDL Motivation. - 3. 2 Parameterized Design with VHDL. - 3. 3 Systematic DwR. - 4 Design for Reuse. - 4. 1 Introduction. - 4. 2 Core Design View. - 4. 3 System Design View. - 4. 4 Simulation Design View. - 4. 5 Cost Model. - 5 Design with Reuse. - 5. 1 Filter Synthesis. - 5. 2 FFT Synthesis. - 6 Board Integration. - 6. 1 Introduction. - 6. 2 Current Design Practice. - 6. 3 Virtual Prototyping. - 6. 4 Board-Level Modeling. - 6. 5 A Case Study. - 6. 6 Conclusion. - 7 Conclusions. - 7. 1 Highlights. - 7. 2 Future Work. - A DwR Software. - A. 1 An ADL-FIR Design. - References. Language: English