VHDL Extensions. - 1. Library Development Using the VHDL-AMS Language. - 2. Behavioral Modeling of Complex Heterogeneous Microsystems. - 3. VHDL-AMS a Unified Language to Describe Multi-Domain Mixed-Signal Designs. Mechatronic Applications. - 4. Efficient Modeling of Analog and Mixed A/D Systems via Piece-Wise Linear Technique. - 5. SUAVE: Object-Oriented and Genericity Extensions to VHDL for High-Level Modeling. - 6. Digital Circuit Design with Objective VHDL. - System Level Design. - 7. UF: Architecture and Semantics for System-Level Multiformalism Descriptions. - 8. Automatic Interface Generation among VHDL Processes in HW/SW Co-Design. - 9. System-Level Specification and Architecture Exploration: An Avionics Codesign Application. - 10. Using SDL to Model Reactive Embedded System in a Co-design Environment. - 11. A Synchronous Object-Oriented Design Flow for Embedded Applications. - 12. Heterogeneous System-Level Cosimulation with SDL and Matlab. - 13. VHDL-Based HW/SW Cosimulation of Microsystems. - 14. Modeling Interrupts for HW/SW Co-Simulation Based on VHDL/C Coupling. - 15. A Comparison of Six Languages for System Level Description of Telecom Applications. - 16. High Level Modelling in SDL and VHDL+. - 17. ECL: A Specification Environment for System-Level Design. - 18. The MCSE Approach for System-Level Design. - Synthesis. - 19. Automatic VHDL Restructuring for RTL Synthesis Optimization and Testability Improvement. - 20. VHDL Dynamic Loop Synthesis. - 21. Hierarchical Module Expansion in a VHDL Behavioural Synthesis System. - Formal Verification. - 22. Port-Stitching: An Interface-Oriented Hardware Specification and VHDL Model Generation. - 23. Formal Verification of VHDL using VHDL-Like ACL2 Models. - 24. Specification of Embedded Monitors for Property Checking. - 25. Formal Specification and Verification of Transfer-Protocols for System-Design in VHDL. Language: English