Analysis of Cache Performance for Operating Systems and Multiprogramming

1 Introduction. - 1. 1 Overview of Cache Design. - 1. 2 Review of Past Work. - 1. 3 Then Why This Research?. - 1. 4 Contributions. - 1. 5 Organization. - 2 Obtaining Accurate Trace Data. - 2. 1 Current Tracing Techniques. - 2. 2 Tracing Using Microcode. - 2. 3 An Experimental Implementation. - 2. 4 Trace Description. - 2. 5 Applications in Performance Evaluation. - 2. 6 Extensions and Summary. - 3 Cache Analyses Techniques An Analytical Cache Model. - 3. 1 Motivation and Overview. - 3. 2 A Basic Cache Model. - 3. 3 A Comprehensive Cache Model. - 3. 4 Model Validation and Applications. - 3. 5 Summary. - 4 Transient Cache Analysis Trace Sampling and Trace Stitching. - 4. 1 Introduction. - 4. 2 Transient Behavior Analysis and Trace Sampling. - 4. 3 Obtaining Longer Samples Using Trace Stitching. - 4. 4 Trace Compaction Cache Filtering with Blocking. - 5 Cache Performance Analysis for System References. - 5. 1 Motivation. - 5. 2 Analysis of the Miss Rate Components due to System References. - 5. 3 Analysis of System Miss Rate. - 5. 4 Associativity. - 5. 5 Block Size. - 5. 6 Evaluation of Split Caches. - 6 Impact of Multiprogramming on Cache Performance. - 6. 1 Relative Performance of Multiprogramming Cache Techniques. - 6. 2 More on Warm Start versus Cold Start. - 6. 3 Impact of Shared System Code on Multitasking Cache Performance. - 6. 4 Process Switch Statistics and Their Effects on Cache ModeUng. - 6. 5 Associativity. - 6. 6 Block Size. - 6. 7 Improving the Multiprogramming Performance of Caches. - 7 Multiprocessor Cache Analysis. - 7. 1 Tracing Multiprocessors. - 7. 2 Characteristics of Traces. - 7. 3 Analysis. - 8 Conclusions and Suggestions for Future Work. - 8. 1 Concluding Remarks. - 8. 2 Suggestions for Future Work. - Appendices. - B. 1 On the Stability of the Collision Rate. - B. 2 Estimating Variations in the Collision Rate. - CInter-Run Intervals and Spatial Locality. - D Summary of Benchmark Characteristics. - E Features of ATUM-2. - E. 1 Distributing Trace Control to All Processors. - E. 2 Provision of Atomic Accesses to Trace Memory. - E. 3 Instruction Stream Compaction Using a Cache Simulated in Microcode. - E. 4 Microcode Patch Space Conservation. Language: English