1. VHDL in 2005 The Requirements. - 2. Application of VHDL Features for Optimization of Functional Validation Quality Measurement. - 3. An Object-Oriented Component Model Using Standard VHDL for Mixed Abstraction Level Design. - 4. A VHDL-Centric Mixed-Language Simulation Environment. - 5. Analogue Circuit Synthesis from VHDL-AMS. - 6. Symbolic Simulation & Verification of VHDL with ACL2. - 7. Functional Verification with Embedded Checkers. - 8. Improved Design Verification by Random Simulation Guided by Genetic Algorithms. - 9. VERIS: An Efficient Model Checker for Synchronous VHDL Designs. - 10. Title On Flip-flop Inference in HDL Synthesis. - 11. Synthesis Oriented Communication Design for Structural Hardware Objects. - 12. High-Level Synthesis through Transforming VHDL Models. - 13. Multi-facetted Modeling. - 14. A Dual Spring System Case-Study Model in Rosetta. - 15. Transformational System Design Based on a Formal Computational Model and Skeletons. - 16. Models of Asynchronous Computation. - 17. A Mixed Event-value Based Specification Model for Reactive Systems. - 18. JESTER: An ESTEREL-based Reactive JAVA Extension for Reactive Embedded Systems. - 19. A Four-phase Handshaking Asynchronous Controller Specification Style and its Idle-Phase Optimization. - 20. Automating the Validation of Hardware Description Language Processing Tools. - 21. A Retargetable Software Power Estimation Methodology. - 22. Performance Tradeoffs for Emulation Hardware Acceleration and Simulation. - 23. TCL PLI a Framework for Reusable Run Time Configurable Test Benches. - 24. Object-Oriented Specification and Design of Embedded Hard Real-Time Systems. - 25. System Level Design for SOC's. - 26. Virtual Component Reuse and Qualification for Digital and Analogue Design. - 27. Interface Based Design Using the VSI System-level Interface Behavioral Documentation Standard. - 28. Virtual Component HW/SW Co-Design. From System Level Design Exploration to HW/SW Implementation. Language: English